AMD begins shipping TSMC 2nm EPYC Venice server CPUs with up to 256 cores

AMD has begun shipping its new EPYC Venice server processors, the first EPYC products built on TSMC's 2-nanometre (N2) process. The top configuration offers up to 256 cores and 512 threads, targeting the growing demand for agentic AI workloads.

2nm process and advanced packaging

According to TrendForce, citing Commercial Times, Venice uses TSMC's N2 process with CoWoS-L advanced packaging, while its I/O dies use a 6nm process. The first shipments are Venice SP7 processors, with the enterprise-focused SP8 platform expected to follow in the first half of 2027. High-frequency models reach up to 5.3GHz. Taiwanese supply-chain partners including TSMC, ASE, SPIL and Powertech Technology are expected to support the new generation.

Aimed at agentic AI and rack-scale systems

At an event on November 10, AMD also introduced Helion rack configurations that extend its sixth-generation EPYC processors into rack-scale AI systems designed to run many AI agents at once. High-density configurations support up to 73,728 threads per rack, with more than 10 certified configurations and initial shipments expected to begin in November. Partners include Foxconn, Compal, Inventec and Wiwynn. AMD expects the addressable data centre CPU market to grow from US$26 billion in 2025 to US$220 billion by 2030.

Roadmap ahead: Verano and A14

Under the current roadmap, the Verano and Venice-X platforms are scheduled to ship in the second half of 2027, with Verano set to adopt TSMC's N2P node. The Zen 7 architecture is expected to arrive in 2028 on TSMC's A14 process. Sources: TrendForce, Commercial Times, The Next Platform.