Tesla unveils new AI chip roadmap: SI6 targets 80x the compute of current chip, Dojo training chip returns

Tesla has disclosed a revamped in-house AI accelerator roadmap, setting a first concrete performance target for its sixth-generation inference chip and confirming that the Dojo training chip, once paused, will return with an entirely new architecture. According to Tom's Hardware, reporting on a Tesla presentation on November 6, the new chips adopt 'Super Intelligence' (SI) branding, with the AI4, AI5 and AI6 generations renamed SI4, SI5 and SI6.

SI6: 80x the compute of the current chip, due 2029-2030

Under the roadmap, the sixth-generation inference chip, the SI6, targets 80 times the compute of the current fourth-generation SI4 (HW4) and nine times the memory (about 144GB), on a Samsung 2nm-class process with multi-chip module packaging, due in 2029-2030. Tesla has signed an agreement with Samsung Foundry to build the sixth-generation inference accelerator through 2033. Tesla did not disclose absolute compute figures: the 80x figure is relative to HW4. Estimates derived from Elon Musk's earlier statements put HW4 at roughly 216 to 576 TOPS, which would imply about 17,000 to 46,000 TOPS for the SI6 — an estimate, not an official figure; real performance can only be verified when the product arrives. The fifth-generation SI5 targets about 40 times the compute of SI4 with 96GB of memory, split between TSMC's 3nm-class and Samsung's 2nm-class processes.

Dojo 3 returns, dropping wafer-scale integration for chiplets

On the training side, the third-generation Dojo (D3) abandons the wafer-scale integration and distributed on-chip SRAM architecture of the first generation in favour of a chiplet design combining 2.5D and 3D packaging with stacked high-bandwidth memory (HBM). Tesla disclosed no compute, memory, process or schedule for D3. The Dojo team was dissolved in August 2025 and the project paused; Musk later said that with the AI5 chip design nearly complete, the company had room to restart Dojo, and that D3 and the planned AI7 would be used for 'space-based compute', deployed in ground and orbital data centres.

Nine-month design cadence; AI7, AI8 and AI9 already planned

Musk said on X that Tesla is aiming for a nine-month design cycle for its AI chips, three months shorter than the roughly annual cadence at Nvidia and AMD; the AI5 design is nearly done, AI6 is in its early stages, and the company has already planned AI7, AI8 and AI9. Analysts note the roadmap shows Tesla extending its custom-silicon bet from in-car autonomy into data centres and the Optimus humanoid robot, but the SI6 is still years away and D3's key parameters are undisclosed — the roadmap will only be tested around 2029.

(Sources: Tom's Hardware; Data Center Dynamics; Tesla presentation materials.)