Dutch Firm Axelera Unveils Titania, Its Third-Generation AI Chip Architecture

Dutch artificial intelligence chip company Axelera AI unveiled its third-generation silicon architecture, Titania, on November 12, a chiplet design aimed at the data centre AI inference market. The company says Titania can deliver up to seven times the throughput per watt of the best data centre servers available, at up to one-twentieth of the total cost of ownership, without the 100-kilowatt-plus liquid-cooled racks that today's highest-density GPU systems require.

What Titania is

Titania is Axelera's third-generation architecture, following Metis and Europa. Its core is digital in-memory compute (D-IMC), now with native FP8 and FP4 floating-point support and programmable RISC-V cores. Each Titania chiplet integrates 32 AI cores, 16 compute cores and 128 MB of cluster-shared SRAM, built on TSMC's N4C process, for 1.25 PFLOPS of peak FP8 compute.

Each system-in-package (SiP) holds two Titania chiplets at 400 watts, delivering 2.5 PFLOPS of FP8. Memory is LPDDR6 rather than scarce, costly high-bandwidth memory (HBM), configurable from 128 GB to 2 TB per package with 2,458 GB/s of bandwidth. The AX8 reference server packs eight SiPs into a 4U air-cooled chassis, delivering 20 PFLOPS of FP8 with 1 TB of LPDDR6 at about 6 kW.

Targeting a $110 billion underserved market

Axelera says Titania targets a market today's high-end GPU systems do not serve: the many enterprises and laboratories that already own data centres but cannot house liquid-cooled racks drawing over a hundred kilowatts. Titania will be offered as PCIe cards and OCP-compliant UBB baseboards, built into inference servers by OEM and ODM partners in both air- and liquid-cooled configurations. The company says it has over $300 million in confirmed commitments, with production starting in Q3 2027 and customer deployments committed into early 2028.

Titania is designed in Europe with support from the EuroHPC Joint Undertaking's DARE initiative. Axelera will present a deeper technical look at the architecture at SC26, the supercomputing conference in Chicago, from November 15 to 19.

The numbers still await independent verification

The 7x efficiency and 20x cost figures are vendor targets drawn from simulations of a chip that has not yet taped out, and they have not been independently verified; the comparison baseline is also the company's own choice of existing server configurations. With volume production not due until the second half of 2027, real-world performance remains to be seen.

Sources: Business Wire; Futurum Group; TechPowerUp.