TSMC 2nm wafers reportedly cost $30,000 each as Rapidus slips on ramp

TSMC's 2-nanometre process reportedly costs about $30,000 per 300-millimetre wafer, roughly 50% more than its 3-nanometre process, according to industry reports, while Japanese chipmaker Rapidus is falling behind on its 2nm mass-production schedule, putting the cost and competitive landscape of advanced chipmaking back in focus.

2nm pricing about 50% above 3nm

Reports put TSMC's current 2nm contract rate at about $30,000 per wafer, against a baseline of about $20,000 for 3nm wafers. TSMC commanded 72.5% of global wafer foundry revenue in the second quarter of 2026, a record high. Apple holds the earliest reservations for 2nm capacity, reportedly taking about half of the initial runs for next-generation mobile processors, while Nvidia and AMD face the same cost floor for their next-generation data-centre silicon. TSMC plans to begin commercial customer deliveries from its 2nm lines in the first half of 2027.

Rapidus likely to miss production deadline

Rapidus, meanwhile, has not yet produced a working static random access memory (SRAM) cell, a basic 2nm building block, and missed a summer milestone for doing so, Bloomberg reported on November 10, leaving it likely to miss its goal of starting mass production in the second half of Japan's fiscal 2027, which runs from October 2027 to March 2028. The company is weighing a one-year delay to fiscal 2028. Its IIM-1 pilot line in Chitose, Hokkaido, was affected by particulate contamination. Japan's Ministry of Economy, Trade and Industry will hold a semiconductor project review in December to assess a planned ¥400 billion equity injection for Rapidus. Rapidus chief executive Atsuyoshi Koike has said its 2nm wafers would be priced at about $20,000, roughly $10,000 below TSMC's rumoured $30,000 quote.

Rising costs lift the bar for AI hardware

Analysts note that higher 2nm wafer prices directly raise costs across the AI hardware supply chain, and Samsung's 2nm offering also faces yield consistency problems. Hyperscale data-centre operators and chip designers are actively pursuing second-sourcing strategies to reduce dependence on a single foundry, but viable alternatives remain limited in the near term.