Micron Ditches 4F² DRAM, Bets on 6F² and 3D Stacking

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Micron president and chief technology officer Scott DeBoer said during a decade-long technology roadmap webinar on October 21 that the company has studied 4F² for over two decades — Micron invented it — but sees 'fundamental' scaling problems at the leading edge. He called the claimed density advantage 'a bit of a myth': buildable at older nodes, but costlier and more complex without a meaningful payoff.

Micron will instead extend its proven 6F² architecture and leap to advanced wafer bonding and three-dimensional stacking. The 1-delta DRAM node follows the current 1-gamma node and is set to ramp in the second half of 2027 at the Boise fab, delivering a mid-20% bit-density improvement and designed for HBM5 and vertical HBM. The 1-epsilon node will fully integrate wafer bonding; 3D DRAM development is slotted between the 1-zeta and 1-eta nodes, with High-NA EUV lithography under exploration.

On NAND, Micron will skip a generation, jumping from Gen 9 to G11: over 400 layers, twice Gen 9's bit density and 1.5× I/O speed, also ramping in H2 2027. HBM4 is already in high-volume production at 2.8 TB/s per stack; next comes vertical HBM stacked directly on processors, plus low-power vertical edge inference memory aimed at robots and cars.

Rivals are not following: China's CXMT recently said it intends to commercialize 4F² server DRAM, briefly dragging down Korean memory stocks. Samsung and SK Hynix remain committed to vertical channel transistors for 4F². The referee in this route battle will be yield and cost — and Micron is betting on 3D.