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imec and Lam Research expand partnership to tackle 3D chip and high-NA EUV manufacturing

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Belgian semiconductor research centre imec and Lam Research have expanded their strategic partnership on advanced 3D chip integration and next-generation lithography, aiming to move emerging chip technologies toward commercially viable production.

Belgian semiconductor research centre imec and Lam Research have expanded their strategic partnership to tackle manufacturing challenges in advanced 3D chip integration and next-generation lithography, Intelligent CIO Europe reported on 30 October. The move comes as demand for AI computing infrastructure accelerates and conventional transistor scaling becomes increasingly difficult.

What the collaboration targets

Researchers will investigate manufacturing processes supporting advanced packaging, heterogeneous integration and future memory architectures, combining Lam's deposition and etching technologies with imec's semiconductor research infrastructure. Key research areas include thick dielectric deposition, stress compensation, plasma dicing and high-aspect-ratio etching for increasingly complex three-dimensional memory structures.

The high-NA EUV piece

The partnership also extends to Lam's Aether dry resist technology, designed for high-numerical-aperture extreme ultraviolet lithography, or high-NA EUV. Using imec's advanced lithography facilities, researchers will examine improvements in pattern resolution, sensitivity and defect reduction for future semiconductor manufacturing nodes.

Progress so far and what comes next

Previous joint research demonstrated single-exposure patterning of ruthenium interconnects at 20-nanometre pitch, achieving 100% electrical yield for bridge-sensitive test structures and more than 90% for break-sensitive structures. The companies believe these results could reduce complex multi-patterning requirements while improving manufacturing efficiency. Further development will investigate advanced interconnects and semiconductor architectures, including gate-all-around transistors and complementary field-effect transistors. Neither company disclosed financial terms or a timetable for industrial deployment; for chipmakers, the central challenge remains translating increasingly sophisticated research into reliable, scalable manufacturing processes.

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